At the opening ceremony of the 2026 IICIE International Integrated Circuit Innovation Expo and the Integrated Circuit Innovation Summit held in Shenzhen, Eastern Compute Core Vice President Guo Wei delivered a keynote address titled "The Post-Moore Era: An Eastern Framework for AI Chip Design." His presentation offered forward-looking insights on topics ranging from architectural innovation to ecosystem restructuring to the assembled semiconductor experts and industry leaders.

Guo Wei initiated his remarks by outlining a broad view of international AI infrastructure investment, highlighting the surge in worldwide AI capital expenditure and its influence on chips, models, and applications. AI infrastructure spans data center construction, computational hardware, storage systems, high-speed network connectivity, software platforms, and energy and cooling solutions, with China and the U.S. jointly accounting for over 90% of global investment in this sector.

Chinese tech giants are making substantial increases to their AI budgets. Alibaba has committed at least 380 billion yuan for AI and cloud infrastructure over the 2025-2027 period. ByteDance invested 150 billion yuan in 2025 and plans annual AI investments of no less than 160 billion yuan moving forward, with 60% dedicated to AI chip procurement. Tencent is set to boost its AI spending in 2026, allocating 70 to 100 billion yuan specifically for AI model and infrastructure research and development. Across the Pacific, the four major U.S. cloud providers—Amazon, Google, Microsoft, and Meta—are projected to invest roughly 350 billion U.S. dollars collectively on AI infrastructure in 2025. According to TrendForce, capital expenditures from the world's nine biggest cloud service providers are expected to surge by around 90% year-over-year in 2026, exceeding 886.7 billion U.S. dollars.

Regarding AI large language models, Guo Wei observed that the gap between Chinese models and leading U.S. models is closing, while Chinese open-source models have gained a clear advantage in cost efficiency over American closed-source counterparts. He noted that the U.S. model landscape is dominated by closed-source state-of-the-art systems like Google's Gemini, which pursues native multimodality and a fully self-developed software-hardware stack. In contrast, China distinguishes itself through extreme optimization in open-source models, with notable offerings from DeepSeek, Alibaba's Tongyi Qianwen, ByteDance's Doubao, and Moonshot AI's Kimi each making strides in long-context processing, multimodal capabilities, and coding proficiency.

Guo Wei emphasized the increasingly powerful synergy between model development and chip innovation. Historically, models and chips evolved independently with incremental improvements. Currently, demand-driven requirements and technological breakthroughs are mutually reinforcing, ushering in an era of cooperative innovation. Looking ahead, models and hardware are set to merge into a unified entity, achieving deep integration. Models are demanding more from chips—greater computational power, expanded memory capacity and bandwidth, and reduced latency and total cost of ownership. Meanwhile, chip and system iterations are accelerating model advancements, enabling large models to deploy across cloud, edge, and terminal environments.

He articulated a critical chain: "Decode performance determines the inference efficiency of large models; memory access bandwidth dictates decode efficiency; and token costs determine inference application expenses." As models evolve from the chatbot era to the AI agent era, "smarter models" require high computational power and elevated memory bandwidth, while "lower-cost applications" demand high bandwidth and cost-effective inference solutions.

Guo Wei candidly addressed the three major obstacles confronting domestic AI chips. The first is the computational power barrier, stemming from constraints on advanced process technology and the significant gap between domestic foundry capabilities and overseas standards. The second is the memory wall, where access bandwidth struggles to keep pace with rapidly growing computational power, leading to underutilized processors. The third is the communication bottleneck, which involves delivering greater interconnect bandwidth within limited packaging dimensions.

To overcome these challenges, Eastern Compute Core is pursuing distinct technological solutions. For computational power, the company employs software-defined tiles to enhance hardware utilization and simplify programming complexity. On the memory front, it uses integrated logic-memory system design to deliver exceptional bandwidth and break through the memory wall. Notably, 3D-IC technology reduces interconnect distances from centimeter-scale to micrometer-scale, cutting data transmission power consumption to between 10% and 20% of traditional 2.5D/2D ICs, while boosting pin density per unit area by 100 to 1,000 times. For interconnects, Eastern Compute Core's Infinity Chiplet 3.5D+ technology achieves greater computational power, higher memory bandwidth, and larger interconnect scale within identical packaging size limits.

Guo Wei elaborated on both the advantages and engineering challenges of 3D-IC technology. By vertically stacking along the Z-axis, interconnects between logic and memory chips shrink from centimeter-scale to micrometer-scale, dramatically reducing signal transmission latency. Direct 3D connections between DRAM and logic layers eliminate the need for HBM while increasing computational density per unit. Area-level vertical interconnects expand interface width from N to N². However, 3D-IC faces engineering hurdles including warpage induced by thermal expansion coefficient mismatches, heat dissipation issues from stacked structures—thermal failures account for 55% of all problems in 3D-stacked chips—and yield challenges arising from the multiplicative effects of multi-layer stacking.

Eastern Compute Core has established a clear technical roadmap to address these issues. The company guides thermal design through refined system-level thermal simulation combined with process capabilities, advances full-flow low-temperature bonding techniques to minimize CTE-related warpage, integrates Chip-to-Wafer processes into its product strategy to capitalize on yield advantages, and implements detailed partial-good die screening schemes to increase chip usability.

In concluding his presentation, Guo Wei stated that Eastern Compute Core's "software-defined plus 3D-stacked near-memory computing" framework represents a distinctive Eastern approach to developing domestic high-end computing chips without relying on cutting-edge process nodes. As the synergistic spiral of chip-model co-development accelerates, China's AI chip industry is well-positioned to carve out a unique innovation path in the post-Moore era.